Method and apparatus for remote flashing of a bios memory in a data processing system

ABSTRACT

A method and apparatus thereof for flashing a BIOS of a data processing system remotely are provided. A BIOS flash instruction is given remotely from a remote console, transmitted to a microprocessor and a corresponding storage media of the data processing system via network, where the microprocessor is irresponsible for operating system. A BIOS image file is identified correct before performing BIOS of a system microprocessor that is responsible for operating system, where the system microprocessor is usually CPU. BIOS is remotely flashed with this method and apparatus, and since flash operation is performed independently of the operating system of the data processing system, BIOS re-flash can be performed and data processing system can be rebooted even when flash operation is failed or operating system is disable.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 93109435, filed on Apr. 6, 2004.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a method for flashing of a BIOS memoryin a data processing system, and more particularly, to a method forremote flashing of a BIOS memory that is complied with various ofoperating systems, and manages to re-flash with BIOS flash failed.

2. Description of the Related Art

Generally speaking, in order to flash a data processing system, forexample, BIOS flash for a computer, the flashing operation has to beperformed under normally running Operating System. In the case when thePower On Self Test (POST) is not successfully passed or the OperatingSystem is not normally operated, remote BIOS flash is not feasible.

Referring to FIG. 1, a schematic flow chart illustrating a method forflashing a computer BIOS according to prior art technology is depicted.When the BIOS flashing starts to work (step 110), the data processingsystem is booted first (step 102), and the Power On Self Test (POST) issubsequently performed (step 104). If the POST is successfully passed(step 101), the process moves to a step of “entering the OperatingSystem (e.g. DOS, Microsoft Windows, Linux, etc.) (step 106). After thesystem has successfully entered the Operating System, if BIOS flash isrequested by the remote console (step 103), a BIOS image file istransmitted firstly (step 108). Then, it is determined whether the BIOSimage file is correct or not (step 105) and the BIOS is flashed byrunning a flash program (step 112). The system is rebooted after theflash operation is completed (step 114). If the BIOS image file isincorrect, a notification is sent to the remote console (step 116) andthe process is terminated (step 120). On the other hand, if the remoteuser does not request to flash the BIOS, the process is terminated (step120). Therefore, in the prior art, in case the BIOS flashing operationstarts whereas the POST fails, the Operating System fails to work,meaning remote BIOS flash cannot be performed.

Regarding hardware configuration of the prior art technology, referringto the block diagram illustrating BIOS flash operation BIOS as shown inFIG. 5. In the diagram, a remote console 502 is used to send a messagethrough an Ethernet 504 and a network interface card 506, wherein themessage indicates that the remote console opts to flash the BIOS. Asystem processor 522 processes such message with the memory spaceconfigured in the system flash memory 524 and the system random accessmemory (RAM) 526 for flashing the system BIOS. According to a step ofreceiving a remote message to flash BIOS, the message between the dataprocessing system and the network is transmitted through a channelprovided by the system processor 522, thus BIOS can be successfullyflashed only when the Operating System is normally operated. On theother hand, if the system suffers from power surge or some other reasonthat fails BIOS flash, the system processor 522 does not manage toreboot after BIOS flash failure, thus the remote console 502 is not ableto perform BIOS flash via the network.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a method for remotelyflashing BIOS is provided, wherein disability of remote BIOS re-flashcaused by a BIOS flash failure is solved.

According to another aspect of the present invention, a method forflashing BIOS is provided, wherein a BIOS image file to be flashedprovided remotely, bridged with a microprocessor yet not performed withthe operating system thereof, manages to directly or indirectly performBIOS flash and system reboot.

In accordance with the above aspects of the present invention, a dataprocessing system is provided, for remotely flashing a rewritablememory. The data processing system includes a remote console, a firstmicroprocessor module, a second microprocessor module, a network, and anetwork interface. Wherein, after transmitted through the network andconverted by the network interface, the flashing instruction and theflashing content provided by the remote console are received andexecuted by the first microprocessor module which is connected to thenetwork interface, and a subsequent process is performed to flash therewritable memory. In the present invention, the rewritable memory,being rewritable BIOS memory of the CPU, for example, is disposed withthe second microprocessor module. In such case, the rewritable BIOSmemory can be directly flashed by the first microprocessor modulewithout performance of the second microprocessor module. If the firstmicroprocessor module does not serve to directly flash the rewritableBIOS memory function, an alternative method can be used to indirectlyflash the rewritable memory via the BIOS boot block by connecting thesecond microprocessor module thereto. The first microprocessor module ofthe present invention includes a first microprocessor and a firstregister. Usually, the first microprocessor is a microprocessor otherthan the CPU of the computer, and the first register is a memorycorresponding to the first microprocessor, e.g. a flash memory, a RAM,etc. In the present invention, a remote instruction and flashing contentare received via the network for BIOS flash of the CPU, where the firstmicroprocessor serves as a bridge along with the operation of the firstregister., Since the first microprocessor being responsible forperforming memory flash and the second microprocessor and the secondregister thereof to be flashed are independent, the rewritable memory ofthe second microprocessor can be flashed either directly or indirectlyby the first microprocessor, which is irrelevant to the operatingsystem. Even memory flash fails, a flash instruction is able to beremotely re-performed via the first microprocessor by the remote consoleuntil the operating system resumes properly.

Furthermore, a direct method for flashing the rewritable memory of thesecond microprocessor without operation of the second microprocessor isprovided as well in the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart illustrating a remote BIOS flashing operationaccording to the prior art.

FIG. 2 is a flow chart illustrating an indirect BIOS flashing operationaccording to an embodiment of the present invention.

FIG. 3A is a flow chart illustrating a direct microprocessor operationaccording to an embodiment of the present invention.

FIG. 3B is a flow chart illustrating an indirect microprocessoroperation according to an embodiment of the present invention.

FIG. 4 is a flow chart illustrating a remote console operation accordingto an embodiment of the present invention.

FIG. 5 is a schematic block diagram illustrating a system of BIOS flashaccording to the prior art.

FIG. 6A is a schematic block diagram illustrating an indirect remoteBIOS flashing system according to an embodiment of the presentinvention.

FIG. 6B is a schematic block diagram illustrating a direct remote BIOSflashing system according to an embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

The present invention provides a remote console that enables a system'sBIOS to be flashed remotely, and more particularly, provides a methodfor re-flashing BIOS if BIOS flash ever fails. The failure to flash theBIOS properly could lead to a system failure. A BIOS image file to beflashed is provided remotely from the remote console of the BIOSflashing system, where a microprocessor serves as a bridge and bypassesthe operation system, before BIOS is successfully flashed and the dataprocessing system is successfully rebooted.

An indirect method for remotely flashing BIOS is provided in the presentinvention, where a microprocessor serves as a bridge. Since themicroprocessor includes a data register, e.g. flash memory, RAM, etc.,when a BIOS flash is instructed by a remote administrator, themicroprocessor remotely flashes the BIOS thereof.

A direct method and an indirect method of remotely flashing BIOS areprovided according to technology of the present invention. Wherein thedirect method, the microprocessor and the rewritable memory of thesystem are coupled with an interface, where the microprocessor managesto flash the BIOS at arbitrary time. If the system is without theinterface, an alternative indirect method mentioned above is triggeredto flash the BIOS. According to the indirect method for flashing BIOS inthe present invention, BIOS is flashed with the code embedded in theBOOT block thereof, thus BIOS is flashed before POST is terminated.Moreover, the code embedded in the BOOT block is non-versatile after thesystem is fabricated, the BOOT block is never vulnerable and re-flash ofthe BIOS is secured.

Referring to FIG. 2, a flow chart of an indirect BIOS flashing methodaccording to an embodiment of the present invention is illustrated. Thesystem BIOS is a rewritable memory for storing a boot block code, whichserves to run BIOS procedures at each time the system is rebooted. Inthe remote flashing method disclosed by the present invention, the BIOSoperating procedure is depicted in FIG. 2. First, when the BIOS bootblock code is being executed (step 202), if BIOS flash is requested bythe remote console (step 203), a BIOS image file is read from theregister associated with the microprocessor (step 204). Wherein the BIOSimage file is then transmitted through the network and the networkinterface from the remote console. After reading procedure of the BIOSimage file is completed, the BIOS image file is examined whether it iscorrect or not (step 205). If incorrect, the microprocessor is informedof incorrect BIOS image file (step 214). If correct, the BIOS flashingis then performed (step 206). Microprocessor is informed of the flashprocedure whether the process is successful (step 208) or failed (step216), whereas system reboot (step 212) is performed when succeeded.

In the present invention, when BIOS flash is to be remotely flashed bythe system administrator, a BIOS flashing instruction is issued by aremote console to the microprocessor of the system, where BIOS is to beflashed remotely thereof. BIOS is flashed directly as the microprocessorreceives the instruction(referring to FIG. 3A), or is halted untilcommunication with the BIOS boot block performed (referring to FIG. 3B).Referring to FIG. 3A, determining whether BIOS flash instruction isreceived by the microprocessor or not (step 303). If the instruction isreceived, the microprocessor serves as a bridge to extract a BIOS imagefile (step 302). As the BIOS image file is extracted and the image fileis determined correct (step 305), a confirmation message is sent to themicroprocessor, and the procedure proceeds to the step of BIOS flash(step 304). Thereafter, determining whether the BIOS flashing issuccessful or not (step 307), and returning a success or failure messageto the remote console according to the result (step 306 and 314). If theflash is successful, the system is rebooted (step 308), and directmicroprocessor procedure for BIOS flash is terminated (step 320).Whereas for indirect microprocessor operation, referring to FIG. 3B.What is different from the direct method is rebooting the system (step308) right after determining whether BIOS image file is correct (step305), and halting transmission of BIOS image file to the boot block code(step 316) until the BIOS boot block requests for BIOS re-flash (step309). As the boot block code returns BIOS flash results, a successful(step 306) or failed (step 314) message is returned to the remoteconsole, and the microprocessor procedure is terminated (step 320).

FIG. 4 is a flow chart illustrating a remote console procedure accordingto an embodiment of the present invention, depicting either the director indirect method. As the remote console requests to flash the BIOSremotely (step 402), if BIOS flash is found to be performing (step 403),a message of “BIOS is flashing” is displayed (step 414). If the BIOSflashing is not found to be performing, a flashing instruction is sentto the microprocessor (step 404). Then, transmitting a BIOS image fileto the microprocessor from the remote console (step 406), anddetermining whether the microprocessor receives the BIOS image filecorrectly or not (step 405). As the BIOS image file is transmittedcompletely, determining whether the BIOS flash is successful or not(step 407). If successful, a message of “BIOS flashing successful” isdisplayed (step 408). If failed, either retrial of BIOS flash isperformed (step 409), or a message of “BIOS flash failed” is displayed(step 412). If the microprocessor receives an incorrect BIOS image file,determining whether to transmit again (step 401).

Referring to FIG. 6B, a schematic block diagram of a direct remote BIOSflash system according to an embodiment of the present invention isillustrated. In the block diagram of the system configuration accordingto one embodiment of the present invention, data communication and BIOSflash are performed by another microprocessor 612 instead of beingperformed by the system microprocessor that is responsible for operatingsystem 622, i.e. CPU. The program code of the microprocessor 612 isstored in the flash memory 614 of the microprocessor, whereas the BIOSimage file received from the remote console 602 is stored in the RAM 616of the microprocessor. The microprocessor and the system flash memoryare coupled with an interface 613, such that BIOS flash is performedeven when the system microprocessor 622 is disable, or the operatingsystem is disable.

Referring to FIG. 6A, a schematic block diagram of an indirect remoteBIOS flashing system according to an embodiment of the present inventionis illustrated. The difference between system configuration herein andthat of the direct remote BIOS flash system is that the microprocessor612 and the system flash memory 624 are not interfaced directly. Whereasremote BIOS flash is performed via system microprocessor (CPU) 622,system DRAM 626, and the BIOS boot block 624 embedded with the systemflash memory. That is, even the operating system is disable, BIOS flashis still performed as desired.

Although the invention has been described with reference to a particularembodiment thereof, it will be apparent to those skilled in the art thatmodifications to the described embodiment may be made without departingfrom the spirit of the invention. Accordingly, the scope of theinvention will be defined by the attached claims and not by the abovedetailed description.

1. A data processing system apparatus, for performing a flash operationto a rewritable memory remotely, the data processing system apparatuscomprising: a remote console; a network; a network interface; a firstmicroprocessor; a first register; a second microprocessor; and a secondregister; wherein the first microprocessor serves as a bridge betweenthe remote console and the network and the network interface, where aninformation transmitted from the remote console for the flash operationis stored in the first register, in order to flash the rewritable memoryassociated with the second microprocessor along with the secondregister.
 2. The data processing system apparatus of claim 1, whereinthe remote console comprises a remote data processing system.
 3. Thedata processing system apparatus of claim 2, wherein the remote dataprocessing system is selected at least one from a group of: a desktopcomputer, a laptop computer, and a server.
 4. The data processing systemapparatus of claim 1, wherein the network comprises an Ethernet.
 5. Thedata processing system apparatus of claim 1, wherein the networkcomprises a Local Area Network (LAN).
 6. The data processing systemapparatus of claim 1, wherein the network interface comprises a NetworkInterface Card (NIC).
 7. The data processing system apparatus of claim1, wherein the first register comprises at least one of a flash memoryand a Random Access Memory (RAM).
 8. The data processing systemapparatus of claim 1, wherein the first microprocessor comprises aCentral Processing Unit (CPU).
 9. The data processing system apparatusof claim 1, wherein the second register comprises at least one of aflash memory and a Random Access Memory (RAM).
 10. The data processingsystem apparatus of claim 9, wherein the flash operation is performed bythe first microprocessor via the second microprocessor along with theflash memory.
 11. The data processing system apparatus of claim 9,wherein the flash operation is performed directly by the firstmicroprocessor accessing the flash memory.
 12. The data processingsystem apparatus of claim 1, wherein the rewritable memory comprises aBasic Input/Output System (BIOS) chip.
 13. The data processing systemapparatus of claim 12, wherein the rewritable memory comprises twoprogrammable parts, where any one of the programmable parts comprises acopy of a code of the rewritable memory while the flash operation isperformed on the rewritable memory, and only the programmable part thatis unable is performed with the flash operation.
 14. The data processingsystem apparatus of claim 12, wherein the rewritable memory comprises anEEPROM.
 15. The data processing system apparatus of claim 1, wherein thedata processing system is a computer system.
 16. The data processingsystem apparatus of claim 1, wherein the data processing system is acomputer network system.
 17. A method for flashing a Basic Input/OutputSystem (BIOS), being performed when a BIOS memory is not under flashing,the method comprising: extracting a BIOS image file from a firstmicroprocessor, wherein the BIOS image file is transmitted from a remoteconsole, and is stored in a first register associated with the firstmicroprocessor; determining whether the BIOS image file is correct ornot; if the BIOS image file is correct, informing the firstmicroprocessor that the BIOS image file is correct; if the BIOS imagefile is incorrect, the first microprocessor is requested by the remoteconsole for re-sending the BIOS image file; proceeding to a flashingoperation, wherein the BIOS image file is written to the BIOS memorywith the first microprocessor via the second microprocessor along with acorresponding second register; determining whether the flash operationis successful or not; sending a message indicating the flash operationis successful or failed to the first microprocessor; and rebooting thesystem.
 18. The flashing method of claim 17, wherein the secondmicroprocessor is a Central Processing Unit (CPU).
 19. The flashingmethod of claim 17, further comprising executing a Power On Self Test(POST) after the system is rebooted.
 20. A method for flashing arewritable memory, wherein a first microprocessor being responsible forperforming operating system, via a second microprocessor and acorresponding register, repeatedly examines a flash content transmittedremotely via a network, the flash content is stored in the registerafter identified correct, and is written to the rewritable memory by thesecond microprocessor.
 21. The method for flashing the rewritable memoryof claim 20, wherein the first microprocessor is a Central ProcessingUnit (CPU).
 22. The method for flashing the rewritable memory of claim20, wherein the register comprises a flash memory.
 23. The method forflashing the rewritable memory of claim 20, wherein the registercomprises a Random Access Memory (RAM).
 24. The method for flashing therewritable memory of claim 20, wherein the network is an Ethernet. 25.The method for flashing the rewritable memory of claim 20, wherein thenetwork is a Local Area Network (LAN).
 26. A data processing systemsuitable for flashing a rewritable memory with a remote instruction, thesystem comprising: a remote console for providing the remote instructionand a flashing content; a first microprocessor module; a secondmicroprocessor module, associated with the rewritable memory, coupled tothe first microprocessor module; a network; and a network interface,coupled to the network and the second microprocessor module.
 27. Thedata processing system of claim 26, wherein the first microprocessormodule comprises: a first microprocessor, coupled to the networkinterface; and a first register, coupled to the first microprocessor.28. The data processing system of claim 27, wherein the first registercomprises at least one of a flash memory and a Random Access Memory(RAM).
 29. The data processing system of claim 26, wherein an operatingsystem booted by the second microprocessor module via the rewritablememory comprises: a second microprocessor, being coupled to the firstmicroprocessor; and a second register, being coupled to the secondmicroprocessor.
 30. The data processing system of claim 26, wherein anoperating system booted by the second microprocessor module via therewritable memory comprises: a second microprocessor, coupled to thefirst microprocessor; and a second register, coupled to the firstmicroprocessor and the second microprocessor.
 31. The data processingsystem of claim 27, wherein the second register comprises at least oneof a flash memory and a Random Access Memory (RAM).
 32. The dataprocessing system of claim 27, wherein the second microprocessor is aCentral Processing Unit (CPU).
 33. The data processing system of claim26, wherein the remote console comprises a remote data processingsystem.
 34. The data processing system of claim 26, wherein the networkcomprises an Ethernet.
 35. The data processing system of claim 26,wherein the network comprises a Local Area Network (LAN).
 36. The dataprocessing system of claim 26, wherein the network interface comprises aNetwork Interface Card (NIC).